Faaiq Waqar

Student

Faaiq Waqar

School of Electrical and Computer Engineering, Georgia Institute of Technology · Atlanta, GA

I am a PhD Candidate at Georgia Tech advised by Prof. Shimeng Yu at the Microelectronics Research Center (MiRC). My work explores emerging devices, materials, and integration approaches for next-generation computing platforms. Beyond my doctoral studies, I've worked on SoC microarchitecture, digital circuit design, and performance tooling at Microsoft, Arm, Intel, and TSMC. I care deeply about teaching, mentorship, and broadening participation in STEM.

Focus

Research Interests

Amorphous Oxide Semiconductors Ferroelectric Memories FPGAs Random Access Memory Architecture Circuit Simulation

My research interests include modeling, metrology, circuit design, and architecture for emerging amorphous oxide semiconductor and ferroelectric devices, with applications in reconfigurable, memory-centric, and high-performance computational systems.

Courses

Teaching

  • ECE3710: Circuits and Electronics Instructor of Record, Georgia Tech · Jan - May 2026
  • CS6501: Special Topics in Computer Science Guest Lecturer, University of Virginia · Mar 2026
  • ECE6465: Memory Devices Technology Guest Lecturer and Lab Developer, Georgia Tech · Aug - Dec 2025
  • ENGR201/202: AC/DC Electrical Fundamentals Undergraduate Teaching Assistant, Oregon State University · Sep 2021 - Jun 2022

Writing

Journal Publications

2026

Long-context LLM acceleration architecture with M3D memory, systolic array, and vector unit

Architecting Long-Context LLM Acceleration With Packing-Prefetch Scheduler And Ultra-Large Capacity On-Chip Memories

M.-Y. Lee, F. G. Waqar, H. Yang, M. Karim, H. Simka, and S. Yu. IEEE Micro.

Paper
Overlapped and underlapped indium tungsten oxide FET structure comparison

Asymmetric Underlap-Overlap 2T Gain Cell Enabling Voltage-Sensing Readout With Minimized Capacitive Coupling

J. Sonawane, S. Deng, C. Zhang, O. Phadke, F. G. Waqar, S. Datta, and S. Yu. IEEE Electron Device Letters, vol. 47, no. 3, pp. 522-525, 2026.

Paper
Monolithically stackable gain cell memory structure for cache
First author Featured paper

Optimization And Benchmarking Of Monolithically Stackable Gain Cell Memory For Last-Level Cache

F. G. Waqar, J. Kwak, J. Lee, O. Phadke, M. Shon, M. Gholamrezaei, K. Skadron, and S. Yu. IEEE Transactions on Computers, vol. 75, no. 3, pp. 760-775, 2026.

Paper PDF Code
Kolmogorov-Arnold network activation basis illustration

Hardware Acceleration Of Kolmogorov-Arnold Network (KAN) In Large-Scale Systems

W.-H. Huang, J. Jia, Y. Kong, F. G. Waqar, T.-H. Wen, M.-F. Chang, and S. Yu. IEEE Transactions on VLSI Systems.

Paper

2025

Amorphous indium oxide FeFET memory array heat map

Amorphous Indium Oxide Channel FeFETs With Write Voltage Of 0.9 V And Endurance > 1012 For Refresh-Free Embedded Memory

S. G. Kirtania, H. Park, O. Phadke, E. Sarkar, D. Chakraborty, F. G. Waqar, J. Shin, A. I. Khan, S. Yu, and S. Datta. IEEE Transactions on Electron Devices, vol. 72, no. 5, pp. 2691-2699, 2025.

Paper
3D CFET digital compute-in-memory bit cell illustration

3D Digital Compute-In-Memory Benchmark With A5 CFET Technology: An Extension To Look-Up-Table-Based Design

J. Lee, M. Shon, F. G. Waqar, and S. Yu. IEEE Transactions on VLSI Systems, vol. 33, no. 7, pp. 1910-1919, 2025.

Paper

2023

Illustration of refrigerator, lime, and temperature sensor for Bayesian inverse problems tutorial
First author

A Tutorial On The Bayesian Statistical Approach To Inverse Problems

F. G. Waqar, S. Patel, and C. M. Simon. APL Machine Learning, vol. 1, no. 4, article 22, 2023.

Paper PDF

Writing

Conference Publications & Talks

2026

FAB Gain Cell Memory: A Folded Asymmetric Boosted Design To Improve Sense Margin For A Refresh-Free Operation

J. Sonawane, S. Deng, K. Lee, F. G. Waqar, C. Zhang, O. Phadke, S. Datta, and S. Yu. IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, 2026.

First Demonstration Of Bit-Cost-Scalable And BEOL-Compatible Monolithic 4-Tier FeRAM Operating At 125 °C

E. Sarkar, J. Sonawane, H. Park, E. Quezada, K. Lee, D. Chakraborty, J. Shin, F. G. Waqar, C. Zhang, H. J. Lee, M. Tian, S. Trolier McKinstry, V. Narayanan, A. I. Khan, S. Yu, and S. Datta. IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, 2026.

Co-first author

Workload-Derived AC Bias Temperature Instability And Mechanism Contributions In BEOL Oxide Channel DRAM Access Transistors

H. J. Lee, F. G. Waqar, H. Park, C. Zhang, J. Shin, E. Sarkar, H. Kim, C. Im, M. J. Hong, D. Ha, A. I. Khan, S. Yu, and S. Datta. IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, 2026.

First author

Enabling Context-Switchable Monolithic 3D FPGA Design Using Bistable Ferroelectric Inverters

F. G. Waqar, M. Chen, Z. He, Z. Wan, M. Shon, W.-H. Huang, J. Cong, and S. Yu. IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Atlanta, GA, 2026.

Presentation only

Non-Volatile FPGAs And CIM Enabled By Dual-FeFET Memory In 28 nm Foundry Process

M. Chen, F. G. Waqar, J. Jia, V. Garg, and S. Yu. MADCAP Workshop at IEEE FCCM, Atlanta, GA, 2026.

Radiation Reliability Of BEOL-Compatible Ga-Doped Indium Oxide MOSFETs For eDRAM Applications

S. G. Kirtania, C. Zhang, S. E. Wodzro, F. G. Waqar, H. J. Lee, D. Chakraborty, J. D. Yeager, D. E. Wolfe, A. I. Khan, S. Yu, and S. Datta. IEEE International Reliability Physics Symposium (IRPS), Tucson, AZ, 2026.

Omelet: A Packaging-Aware Hierarchical Interconnect Simulator For 2.5D/3D Chiplet Architectures

J. Kim, D. Baig, F. G. Waqar, A. Victor, S. Yu, M. S. Bakir, and C. Hao. ACM/IEEE International Symposium on Computer Architecture (ISCA), Raleigh, NC, 2026.

2025

Co-first author

Demonstration Of 3T0C Gain Cells With Self-Aligned Oxide Transistors For Parasitic-Aware Design At Array-Level

S. Deng, J. Sonawane, F. G. Waqar, O. Phadke, C. Zhang, M.-Y. Lee, S. Yu, and S. Datta. IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, 2025.

Paper
First author Best presentation

CMOS+X: Stacking Persistent Embedded Memories Based On Oxide Transistors Upon GPGPU Platforms

F. G. Waqar, M.-Y. Lee, S. Yoon, S. Lim, and S. Yu. ACM/IEEE International Symposium on Memory Systems (MEMSYS), Washington DC, 2025.

Paper PDF Slides
First author

Monolithic 3D FPGA Design And Synthesis With Back-End-Of-Line Configuration Memories

F. G. Waqar, J. Zhang, A. Lu, Z. He, J. Cong, and S. Yu. ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, 2025.

Paper PDF Slides

Digital Compute-In-Memory Ising Annealer With Ferroelectric Capacitor-Based nvSRAM For Combinatorial Optimization Problems

Y. Kong, J. Jia, A. Lu, F. G. Waqar, Y.-C. Luo, H. Li, I. Young, and S. Yu. IEEE International Symposium on Circuits and Systems (ISCAS), London, UK, 2025.

Paper
Presentation only

Digital Compute-In-Memory Ising Annealer With Ferroelectric Capacitor-Based nvSRAM For Travelling Salesman Problem

Y. Kong, J. Jia, A. Lu, F. G. Waqar, Y.-C. Luo, H. Li, I. Young, and S. Yu. International Workshop on Ising Machines (IISM), Chicago, IL, 2025.

Hardware Acceleration Of Kolmogorov-Arnold Network (KAN) For Lightweight Edge Inference

W.-H. Huang, J. Jia, Y. Kong, F. Waqar, T.-H. Wen, M.-F. Chang, and S. Yu. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2025.

Paper

Radiation-Resilient Amorphous Indium Oxide FeFETs For Embedded Nonvolatile Memory

S. G. Kirtania, F. G. Waqar, D. Chakraborty, J. Shin, E. Sarkar, J. Reiss, D. E. Wolfe, S. Yu, and S. Datta. IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, 2025.

Paper
Presentation only

Experimental Demonstration Of Gain Cells With Self-Aligned Oxide Transistors For Reduced Capacitive Coupling

J. Sonawane, S. Deng, F. G. Waqar, O. Phadke, C. Zhang, M.-Y. Lee, S. Datta, and S. Yu. IEEE Non-Volatile Memory Technology Symposium (NVMTS), Atlanta, GA, 2025.

Paper

2024

First Demonstration Of W-Doped In2O3 Gate-All-Around (GAA) Nanosheet FET With Improved Performance And Record Threshold Voltage Stability

E. Sarkar, C. Zhang, D. Chakraborty, F. Waqar, S. Kirtania, K. A. Aabrar, H. Park, J. Shin, M. Tian, A. I. Khan, S. Yu, and S. Datta. IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, 2024.

Paper

Amorphous Indium Oxide Channel FeFETs With Write Voltage Of 0.9 V And Endurance > 1012 For Refresh-Free 1T-1FeFET Embedded Memory

S. G. Kirtania, O. Phadke, E. Sarker, K. A. Aabrar, D. Chakraborty, F. Waqar, S. Jaewon, T. Pantha, S. Dutta, A. I. Khan, S. Yu, and S. Datta. IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, 2024.

Paper

2023

Presentation only

A Tutorial On The Bayesian Approach To Inverse Problems (Eg, In Heat Transfer)

F. Waqar, S. Patel, and C. Simon. AIChE Annual Meeting, 2023.

2020

Towards Explainable Message Passing Networks For Predicting Carbon Dioxide Adsorption In Metal-Organic Frameworks

A. Raza, F. Waqar, A. Sturluson, C. Simon, and X. Fern. ML4Molecules Workshop at NeurIPS, 2020. arXiv:2012.03723.

Paper PDF

Beyond Research

Service

Opportunity Research Scholars students presenting posters

Opportunity Research Scholars Mentor

Sep 2025 - Present

I mentor undergraduate ECE students through the Opportunity Research Scholars Program, an enrichment research program that helps students connect classroom concepts with real applications and build research confidence.

Systems Poster Devices Poster
  • ECE Graduate Student Association President; Electrical and Computer Engineering Graduate Representative Aug 2024 - Present · Georgia Institute of Technology
  • Journal/Conference Reviewer Service Aug 2023 - Present IEEE International Symposium on Workload Characterization (IISWC) IEEE Electron Device Letters (EDL) Future Generation Computer Systems
  • Graduate Student Government Association Academic and Research Affairs Committee Member Aug 2023 - Aug 2024 · Georgia Institute of Technology
  • EECS Senior Capstone Project Partner and Mentor Sep 2022 - Jun 2023 · Oregon State University
  • Beaverton School District FIRST Robotics Mentor Sep 2022 - Jun 2023 · Oregon State University

Background

Education

  • Georgia Institute of Technology Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering; minors in Physics and Education 2023 - 2027
  • Oregon State University Bachelor of Science (B.S.), Electrical & Computer Engineering Bachelor of Science (B.S.), Computer Science; minor in Mathematics 2017 - 2022

Industry

Experience

  • Corporate Research Intern Intern
    TSMC May 2026 - Aug 2026 · San Jose, CA
  • Hardware Engineer Full-time
    Microsoft Jul 2022 - Aug 2023 · Portland, OR SoC microarchitecture and digital circuit design for custom silicon server products
  • CPU Engineering Intern Intern
    Arm Jun 2021 - Sep 2021 · Austin, TX Tool infrastructure for performance and validation of next-generation cores
  • Client Computing Group Intern Intern
    Intel Corporation Nov 2016 - Feb 2017 · Hillsboro, OR Client computing support, operations, and technical issue routing

Recognition

Awards

  • NSF Graduate Research Fellow Fellowship
    National Science Foundation
  • President's Fellowship Fellowship
    Georgia Institute of Technology
  • Best Presenter Award
    ACM/IEEE International Symposium on Memory Systems
  • DAC Young Fellowship Fellowship
    IEEE Design Automation Conference
  • CREATION Award Award
    Georgia Institute of Technology
  • STEER Fellowship Fellowship
    Georgia Institute of Technology
  • Undergraduate Research Fellow Award
    Oregon State University Office of Undergraduate Research and the Arts
  • Undergraduate Research (URSA) Engage Award Award
    Oregon State University